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Please use this identifier to cite or link to this item: http://ri.uaemex.mx/handle20.500.11799/39158
DC FieldValueLanguage
dc.creatorJesús Ezequiel Molinar Solis-
dc.creatorRODOLFO ZOLA GARCIA LOZANO-
dc.creatorVICTOR HUGO PONCE PONCE-
dc.creatorALEJANDRO DIAZ SANCHEZ-
dc.creatorJOSE MIGUEL ROCHA PEREZ-
dc.date2010-
dc.identifierhttp://hdl.handle.net/20.500.11799/39158-
dc.descriptionThis work provides an accurate methodology for extracting the floating-gate gain factory, of CMOS floating-gate inverters with a clock-driven switch for accessing temporarilly to the floating-gate. With the methodology proposed in this paper, the γ factor and other parasitic capacitances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This parameter plays an important role in modern analog and mixed-signal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMI-ABN process with 1.2 µm design rules, were compared. The extracted parameters can be incorporated into floating-gate PS pice macromodels for obtaining accurate electrical simulation.-
dc.formatapplication/application/pdf-
dc.languageeng-
dc.publisherUniversidad Nacional Autónoma de México-
dc.relationhttp://www.redalyc.org/revista.oa?id=404-
dc.rightsinfo:eu-repo/semantics/openAccess-
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0-
dc.sourceIngeniería. Investigación y Tecnología (México) Num.3 Vol.XI-
dc.subjectIngeniería-
dc.subjectFG-inverter-
dc.subjectneuMOS-
dc.subjectfloating-gate-
dc.subjectinfo:eu-repo/classification/cti/7-
dc.titleElectrical parameters extraction of CMOS floating-gate inverters-
dc.typearticle-
dc.audiencestudents-
dc.audienceresearchers-
item.grantfulltextnone-
item.fulltextNo Fulltext-
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