A low-complexity current-mode WTA circuit based on CMOS Quasi-FG inverters

Please use this identifier to cite or link to this item: http://ri.uaemex.mx/handle20.500.11799/39483

DC Field	Value	Language
dc.creator	Jesús Ezequiel Molinar Solis	-
dc.creator	LUIS ABRAHAM SANCHEZ GASPARIANO	-
dc.creator	RODOLFO ZOLA GARCIA LOZANO	-
dc.creator	VICTOR HUGO PONCE PONCE	-
dc.creator	JUAN JESUS OCAMPO HIDALGO	-
dc.creator	HERON MOLINA LOZANO	-
dc.creator	ALEJANDRO DIAZ SANCHEZ	-
dc.date	2011	-
dc.identifier	http://hdl.handle.net/20.500.11799/39483	-
dc.description	In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with logical outputs is presented. The proposed approach employs a Quasi-FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double-poly, three metal layers, 0.5µm CMOS technology. The circuit exhibits a good accuracy-speed tradeoff when compared to other reported WTA architectures.	-
dc.format	application/application/pdf	-
dc.language	eng	-
dc.publisher	Instituto Politécnico Nacional	-
dc.relation	http://www.redalyc.org/revista.oa?id=615	-
dc.rights	info:eu-repo/semantics/openAccess	-
dc.rights	http://creativecommons.org/licenses/by-nc-nd/4.0	-
dc.source	Computación y Sistemas (México) Num.3 Vol.14	-
dc.subject	computación	-
dc.subject	winner-take-all	-
dc.subject	neural networks	-
dc.subject	analog circuits	-
dc.subject	info:eu-repo/classification/cti/7	-
dc.title	A low-complexity current-mode WTA circuit based on CMOS Quasi-FG inverters	-
dc.type	article	-
dc.audience	students	-
dc.audience	researchers	-
item.grantfulltext	none	-
item.fulltext	No Fulltext	-
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