Electrical parameters extraction of CMOS floating-gate inverters

Please use this identifier to cite or link to this item: http://ri.uaemex.mx/handle20.500.11799/39158

Title:	Electrical parameters extraction of CMOS floating-gate inverters
Keywords:	Ingeniería;FG-inverter;neuMOS;floating-gate;info:eu-repo/classification/cti/7
Publisher:	Universidad Nacional Autónoma de México
Project:	http://www.redalyc.org/revista.oa?id=404
Description:	This work provides an accurate methodology for extracting the floating-gate gain factory, of CMOS floating-gate inverters with a clock-driven switch for accessing temporarilly to the floating-gate. With the methodology proposed in this paper, the γ factor and other parasitic capacitances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This parameter plays an important role in modern analog and mixed-signal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMI-ABN process with 1.2 µm design rules, were compared. The extracted parameters can be incorporated into floating-gate PS pice macromodels for obtaining accurate electrical simulation.
Other Identifiers:	http://hdl.handle.net/20.500.11799/39158
Rights:	info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc-nd/4.0
Appears in Collections:	Producción

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