Please use this identifier to cite or link to this item:
http://ri.uaemex.mx/handle20.500.11799/39483| Title: | A low-complexity current-mode WTA circuit based on CMOS Quasi-FG inverters | Keywords: | computación;winner-take-all;neural networks;analog circuits;info:eu-repo/classification/cti/7 | Publisher: | Instituto Politécnico Nacional | Project: | http://www.redalyc.org/revista.oa?id=615 | Description: | In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with logical outputs is presented. The proposed approach employs a Quasi-FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double-poly, three metal layers, 0.5µm CMOS technology. The circuit exhibits a good accuracy-speed tradeoff when compared to other reported WTA architectures. | Other Identifiers: | http://hdl.handle.net/20.500.11799/39483 | Rights: | info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc-nd/4.0 |
| Appears in Collections: | Producción |
Show full item record
Google ScholarTM
Check
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.